Method and arrangement for sample-rate conversion

ABSTRACT

Method and arrangement for converting the sample rate of a higher sample rate discrete time signal to a lower sample rate discrete time signal or vice versa. A recursive signal processing algorithm with low pass filtering function is used, which entirely takes place at the lower sample rate. The impulse response of the low pass filtering function is a power series expansion

The invention relates to a method of converting the sample rate of adiscrete-time input signal with sample rate q.f_(s) to a discrete-timeoutput signal with a sample rate f_(s) which is a sub multiple of thesample rate of the input signal (q=integer larger than 1), the methodcomprising the steps of series to parallel converting the input signalto generate non-overlapping words of q samples of the input signal andof processing said words at the sub multiple rate f_(s) in accordancewith a recursive algorithm comprising a low-pass filtering function.Such method is known from the article “Recursive Bitstream Conversion”by E. Roza in IEEE Transactions on Circuits and Systems-II: Analog andDigital Signal-Processing, Vol. 40, NO 2, February 1993. The inventionfurther relates to the reverse method of converting the sample rate of adiscrete-time input signal with sample rate f_(s) to a discrete-timeoutput signal with a sample rate q.f_(s) which is a multiple of thesample rate of the input signal (q=integer larger than 1), the methodcomprising the steps of processing said input signal at the sample ratef_(s) in accordance with a recursive algorithm comprising a low-passfiltering function to obtain non-overlapping words of q samples of theoutput signal and of parallel to series converting said words togenerate the discrete-time q.f_(s) sample rate output signal.

The above-described methods have become known under the name: “Rebic”(recursive bit-stream conversion) and in this application the expression“forward Rebic” shall be used for the conversion of a low-precision highsample rate signal to a high precision low sample rate signal, while theexpression “reverse Rebic” shall be used for the conversion of a highprecision low sample rate signal to a low precision high sample ratesignal. The low precision high rate signal may often be a “single bit”bitstream, where each sample comprises only one bit, although thissignal occasionally may comprise more than one bit per sample.

Usually the generation of a “single bit” bitstream, either from ananalog input signal or from a high precision low sample rate discretesignal, is done by a conventional ΣΔ modulator, which basically consistsof a low pass filter and a clock-synchronized quantizer in feedbackarrangement. This is a low cost and robust arrangement for performingthe conversion. However, when signals with large base-bandwidth, such ase.g. video signals, have to be converted, the sample rate has to beextremely high in order to obtain sufficient noise shaping and thenseveral drawbacks of the conventional ΣΔ modulator become apparent. Thebasic advantage of the above-described Rebic configuration is that ithas a loop-configuration that operates at the lower clock rate, which isa fraction (1/q) of the clock rate that is required in conventional ΣΔmodulators. An out-of-loop parallel-to series converter is necessary andsufficient to produce a serial bitstream with similar properties asobtained from conventional configurations. The advantages of Rebic overconventional ΣΔ modulators are: reduction of high-speed circuitry, lowerpower consumption, less interference tones and increased stability inhigh-order configurations.

In the above referenced article the low-pass filter operation isachieved by an expansion of its impulse response into a series ofexponential functions. In contradistinction, the present invention isbased on the recognition that such exponential expansion is notobligatory and the method of sample rate conversion according to thepresent invention is therefore characterized in that the algorithm isbased on a power-series expansion of the impulse-response of thelow-pass filtering function. Such impulse responses may be obtained fromdiscrete-time integrators and can therefore be obtained from actualdigital circuitry more easily than conventional impulse responses.Preferably, the method according to the invention, both for the forwardRebic conversion and for the reverse Rebic conversion, is characterizedin that the said processing is in accordance with the formulas (1) to(3e) of the accompanying formula sheet, wherein a_(n) represents thesequence of samples of the discrete-time signal with sample rateq.f_(s), wherein b_(j) represents the sequence of samples of thediscrete time signal with sample rate f_(s), wherein α_(m) represent thecoefficients of the power series of the impulse response of the low-passfiltering function and α_(m)′ the said coefficients divided by the sumof all said coefficients. In this algorithm it is assumed that theimpulse response of the low pass filtering function

${{h(t)} = {{U(t)}{\sum\limits_{m = 0}^{M}{\alpha_{m}( {t/T} )}^{m}}}},$which implies that the impulse response is zero at time t=0. Hereafterit will be shown that also other power series expansions of the impulseresponse may be used.

The invention also relates to an arrangement for sample rate conversion,which arrangement then usually comprises a number of integrators (I₂-I₃,I₄-I₅-I₆) in cascade i.e. that a former integrator in the cascade sendsits output signal, together with one or more other signals, to the nextintegrator in the cascade. The Rebic structure may be of certain order,which is the order of the low pass filter function used in the Rebicalgorithm. Normally the number of cascaded integrators in a low passfilter determines the order of the filter. This also applies to theRebic algorithm. However it appears that, in case of a forward Rebicstructure, one of the integrators is redundant so that the arrangementmay preferably be characterized in that the number of integrators in thecascade of integrators is one less than the order of the algorithm.

It appears that in a reverse Rebic structure according to the inventionit is not possible to calculate the samples a_(n) of the high samplerate signal directly from the samples of the low sample rate signal.From equation (3c) of the enclosed formulas sheet it follows that thesequence a_(n) is hidden in the sum Σα_(m)′A_(mj), which is hereincalled the “bunch value” at the time j. In order to derive said sequencethe reverse basic structure according to the invention is furthercharacterized by comprising a mapper receiving a mapper input signalfrom said integrators in cascade and generating said non-overlappingwords of q samples of the output signal. The task of the mapper is toestablish a q-length binary sequence a_(n) such that the bunch valueΣα_(m)′A_(mj) is close to the mapper input sequence. Because there are2^(q) possible binary sequences of length q, there are also 2^(q) valuesof the bunch value to which the mapper input sequence will be mapped.One possible strategy could be to compare the most recent value of themapper input sequence with a predefined table of all possible bunchvalues on the basis of a best fit. However, this can be quite cumbersomefor large values of q. Therefore a preferred reverse Rebic structureaccording to the invention may preferably be characterized in that saidmapper comprises a cascade of quantizer-subtracter combinations, each ofsaid combinations comprising a 1-bit quantizer for generating one of thebits of said non-overlapping words of q bits and a subtracter forsubtracting the input- and output-signals of the 1-bit quantizer, thatthe first of said combinations in the cascade receives the mapper inputsignal, that each of the other of said combinations in the cascadereceives a weighed sum of the output signals of the subtracters of theprevious combinations in the cascade and that a final quantizer receivesa weighed sum of the output signals of all subtracters in the cascadeand generates the final bit of said non overlapping words of q bits.

Further, in order to prevent the Rebic structure from becoming unstable,the arrangement according to the invention may further be characterizedin that at least one of said integrators comprises a clipper.

The invention will be described with reference to the accompanyingformula sheet and to the accompanying figures. Herein shows:

FIG. 1 an embodiment of a forward Rebic sample rate converter accordingto the invention,

FIG. 2 an embodiment of a reverse Rebic sample rate converter accordingto the invention,

FIG. 3 an embodiment of a mapper for use in the reverse Rebic samplerate converter of FIG. 2,

FIG. 4 a modification of part of the reverse Rebic sample rate converterof FIG. 2 and

FIG. 5 a modification of an integrator for use in a Rebic sample rateconverter according to the invention.

The algorithm used for the sample rate conversion is based on equatingthe response of the low pass filter operation to the high sample ratesignal a_(n) with the response of the said low pass filter operation tothe low sample rate signal b_(j). The impulse response of the low passfilter operation is an expansion in terms of a power series and may beexpressed by the following formula:

${h(t)} = {{U(t)}{\sum\limits_{m = 0}^{M}{{\alpha_{m}( {t/T} )}^{m}.}}}$Herein is U(t) Heaviside's step function, M defines the order of thefilter and α_(m) are the filter coefficients that can freely be chosen.When the two mentioned responses are equated the formula (1) of theformula sheet is obtained. In formula (2) this equation is split intofour terms respectively representing from left to right: the most recentsample of the signal b_(j), the filtered contribution from the q mostrecent samples of the signal a_(n), the filtered history of the signala_(n) and finally the filtered history of the signal b_(j).

In formula (2a) the coefficients α_(m) are replaced by the normalizedcoefficients α_(m)′ that are obtained by dividing each coefficient α_(m)by the sum of all coefficients, with the result that

${\sum\limits_{m = 0}^{M}\alpha_{m}^{\prime}} = 1.$When A_(ij) and r_(ij) are defined as shown in formulas (3a) and (3b),the formula (2a) for b_(j) becomes

$b_{j} = {\sum\limits_{m = 0}^{M}{\alpha_{m}^{\prime}( {A_{mj} + r_{mj}} )}}$as is shown in formula (3c). The value r_(mj) may be recursivelyexpanded so as to obtain the equation (3d) wherein the signal T_(ij) isdefined by equation (3e). The symbol (_(i) ^(m)) in equation (3d) standsas usual for the binomial coefficient

$\frac{m!}{{i!}{( {m - i} )!}}.$The set of equations (3a) . . . (3e) easily allows to determine astructure for implementing the algorithm, as will be shown afterwardswith reference to FIGS. 1, 2 and 3.

The value of M determines the order of the Rebic. A 3^(rd) order Rebicis obtained when M=2, a 4^(th) order is obtained when M=3 and so on.Usually a filter of certain order requires an equal number of cascadedintegrators. However, it appears that, in a forward Rebic, one of suchintegrators is redundant so that the number of cascaded integrators canbe one less than the order of the Rebic. This follows from the formulas(4a) and (4b) of the formulas sheet. Formula (3c) represents the basicequation from which the new sample b_(j) is calculated. One sampleperiod earlier the sample b_(j-1) has been calculated by thecorresponding formula (4a). Because

${\sum\limits_{m = 0}^{M}\alpha_{m}^{\prime}} = 1$the term b_(j-1) in this formula can be brought between the brackets, sothat, using the T_(ij)-definition of formula (3e), the equation (4b) isobtained. This equation allows to calculate the last term T_(Mj) withoutan integrator, when all other terms T_(0j . . .) T_((M-1)j) are obtainedthrough integration.

FIG. 1 shows a structure for the implementation of the algorithm for thecase that M=2, {α_(m)}={0, α₁, α₂}and q=4. Structures for othercombinations of M, α_(m) and q can be readily established. In practicelarger values of q will usually be applied. With these values for M andα_(m) the formula (3c) for b_(j) becomes as is shown in formula (5a).Because from equation (3d) it follows that r_(0j)=T_(0j),r_(1j)=T_(0j)+T_(1j) and r_(2j)=T_(0j)+2T_(1j)+T_(2j) the equation (5a)can be rewritten as shown in equation (5b). A structure for calculatingb_(j) in accordance with this formula would require (at least) threeintegrators. However, with equation (4b) it is follows thatα₁′T_(1j)+α₂′T_(2j)=0 so that equation (5b) simplifies to equation (5c).

The left-hand part of FIG. 1 shows a series to parallel converter SPwith 1-bit latches L, with which non-overlapping (“isolated”) words of q1-bit symbols of a_(n) are down-sampled with a factor q. The words of qbits are applied to an adder D₀ for generating the signal A_(0j), to aset of multipliers M₁ and an adder D₁ for generating the signal A_(1j)and to a set of multipliers M₂ and an adder D₂ for generating the signalA_(2j). The multipliers M₁ multiply the bits with the weighing factors1/q, 2/q, 3/q . . . q/q respectively and the multipliers M₂ multiplythese bits with the weighing factors (1/q)², (2/q)², (3/q)² . . . (q/q)²respectively, so that the generation of the signals A_(0j), A_(1j) andA_(2j) is in accordance with formula (3a).

A subtracter S₁ generates the signal A_(0j)-b_(j) that is applied to anintegrator I₁. This is a “delaying” integrator, which has a Z-transform1/(z-1) i.e. which has a 1-sample delay in its forward path and no delayin its feedback path. This is in contradistinction with a “non delaying”integrator, which has a Z-transform z/(z-1) i.e. which has a 1-sampledelay in its feedback path and no delay in its forward path. Thedelaying integrator I₁ outputs the previous sample of the input signalplus the previous sample of the output signal. It easily follows fromequations (3d) and (3e) that the output of integrator I₁ is then equalto A_(0(j-1))−b_((j-1))+r_(0(j-1))=T_(0j)=r_(0j). This signal is addedto A_(1j) in an adder D₃ and the result is multiplied in a multiplier M₃with the weighing factor α₁′ to obtain the signal α₁′(A_(1j)+T_(0j)).

A second subtracter S₂ and a second delaying integrator I₂ receive thesame input signals as the subtracter S₁ and the integrator I₁ andconsequently they generate the same output signal T_(0j). A subtracterS₃ subtracts the signals A_(1j) and b_(j) and in an adder D₄ the resultis added to the output T_(0j) of integrator I₂ to generate the signalA_(1j)−b_(j)+T_(0j). This is applied to a third delaying integrator I₃.From equations (3d) and (3e) it can be derived that integrator I₃generates the signal T_(1j)=A_(1(j-1))−b_(j-1)+T_(0(j-1))+T_(1(j-1)).

A multiplier M₄ multiplies the signal T_(1j) with the factor 2 and anadder D₅ adds the signal A_(2j) from the adder D₂, the signal T_(0j)from the integrator I₂ and the signal 2T_(1j) from the multiplier M₄together to generate the signal A_(2j)+T_(0j)+2T_(1j), which issubsequently multiplied in a multiplier M5 by the weighing factor α₂′ togenerate the signal α₂′(A_(2j)+T_(0j)+2T_(1j)). The signals from themultipliers M₃ and M₅ are finally added in an adder D₆ to obtain theoutput signal b_(j) in accordance with equation (5c) of the formulassheet.

It has to be noted, that the structure of FIG. 1 may be modified inseveral ways with the same end-result. For instance, the subtracter S₁and the integrator I₁ can be deleted while the signal T_(0j) for theadder D₃ can be obtained from the output of integrator I₂. Furthermore,the adders D₃, D₅, D₆ and the multipliers M₃, M₄ and M₅ can be replacedby a multiplier for multiplying the signal A_(1j) from the adder D₁ byα₁′, a multiplier for multiplying the signal A_(2j) from the adder D₂ byα₂′, a multiplier for multiplying the signal T_(1j) from integrator I₃by 2α₂′ and a single adder for adding the signals from these threemultipliers and the signal T_(0j) from integrator I₂ together to obtainthe signal b_(j)=α₁′A_(1j)+α₂′A_(2j)+T_(0j)+2α₂′T_(1j). This expressionis equal to that of formula (5c) because α₁′+α₂′=1.

The reverse Rebic process implies the determination of a bitstream a_(n)from a given high precision multibit sequence b_(j). The formulas (1) to(3e) of the formulas sheet equally apply to the reverse Rebic of thisinvention, although formula (3c) is preferably written as:

${{\sum\limits_{m = 0}^{M}{\alpha_{m}^{\prime}A_{mj}}} = {b_{j} - {\sum\limits_{m = 0}^{M}{\alpha_{m}^{\prime}r_{mj}}}}},$thereby indicating that the “bunch-value”

$\sum\limits_{m = 0}^{M}{\alpha_{m}^{\prime}A_{mj}}$is calculated from the input sequence b_(j) and the calculated sequence

$\sum\limits_{m = 0}^{M}{\alpha_{m}^{\prime}{r_{mj}.}}$It is clear that this formula does not allow to calculate a_(n)directly, because the sequence a_(n) is hidden in the bunch value

$\sum\limits_{m = 0}^{M}{\alpha_{m}^{\prime}{A_{mj}.}}$Therefore a mapping process is needed to assign a particular word of qbits for each bunch value

$\sum\limits_{m = 0}^{M}{\alpha_{m}^{\prime}{A_{mj}.}}$Several strategies for this mapping process are possible, such as “bestfit, binary search”, see the article “Recursive Bitstream Conversion,the reverse mode.” By E. Roza in ”IEEE Transactions on Circuits andSystems, vol. 41, no.5, pp. 329–336, May 1994 or ”recursive mapping”,see the article “Reduced-sample-rate sigma-delta modulation usingrecursive deconvolution.” by D. Birru in “Int. Journal of Circuit Theoryand Applications”, vol. 25, pp. 419–437, 1997. So, once the value of

$\sum\limits_{m = 0}^{M}{\alpha_{m}^{\prime}A_{mj}}$has been determined and mapping has taken place, a parallel to seriesconversion of bunches of q bits is necessary and sufficient to obtain qconsecutive bits of the bitstream a_(n).

FIG. 2 shows a possible structure for the implementation of the reverseRebic process. To facilitate the comparison with the forward Rebic ofFIG. 1, the same parameters M=2, {α_(m)}={0, α₁, α₂} and q=4 have beenchosen for the reverse Rebic of FIG. 2. A subtracter S₄ receives thesignals b_(j) and A_(0j) and generate there from the differenceb_(j)−A_(0j). This signal is integrated to the signal −T_(0j) in thedelaying integrator I₄. A subtracter S₅ and an adder D₇ generate thesignal b_(j)−A_(1j)−T_(0j) and a delaying integrator I₅ integrates thissignal to the output signal −T_(1j). A multiplier M₆ doubles this signalto −2T_(1j). A subtracter S₆ and a one-sample delay F generate from thetwo signals A_(2j) and b_(j) the output signal b_((j-1))−A_(2(j-1)) andthis signal is, together with the signal −2T_(1j) from the multiplier M₆and the signal −T_(0j) from the integrator I₄, added in an adder D₈ andsubsequently supplied to a non-delaying integrator I₆ to generate thesignal −r_(2j) at the output thereof. Moreover, the signals −T_(0j) fromthe integrator I₄ and the signal −T_(1j) from the integrator I₅ areadded in an adder D₉ to generate the signal −r_(1j).

The signals b_(j) and −r_(1j) are added in an adder D₁₀ and multipliedby the coefficient α₁′ in a multiplier M₇ to obtain the signalα₁′{b_(j)−r_(1j)}. Equally, the signals b_(j) and −r_(2j) are added inan adder D₁₁ and multiplied by the coefficient α₂′ in a multiplier M₈ toobtain the signal α₂′{b_(j)−r_(2j)}. α₂′{b_(j)−r_(2j)}. Finally the twooutput signals of the multipliers M₇ and M₈ are added in an adder D₁₂ toobtain the mapper input signal b_(j)−α₁′r_(1j)−α₂r_(2j), which,according to equation (5a) of the formulas sheet, should correspond withthe bunch value

${\sum\limits_{m = 0}^{2}{\alpha_{m}^{\prime}A_{mj}}} = {{{\alpha_{1}^{\prime}A_{1j}} + {\alpha_{2}^{\prime}A_{2j}}}..}$The mapper P generates during each sample period at its output aparallel word of q bits which, when put in series, represents q bits ofthe output signal a_(n). The weighted sum of the mapper output signalsis the bunch value

${{\sum\limits_{m = 0}^{2}{\alpha_{m}^{\prime}A_{mj}}} = {{\alpha_{1}^{\prime}A_{1j}} + {\alpha_{2}^{\prime}A_{2j}}}},$which should be as close as possible to the mapper input signal b_(j).This will be guaranteed by a correctly designed mapper.

The mapper P generates during each sample period at its output aparallel word of q bits which, when put in series, represents q bits ofthe output signal a_(n). This parallel word of q bits is applied to aparallel to series converter PS for conversion to the high sample ratesignal a_(n), to an adder D₁₃ for generating the signal A_(0j), to a setof multipliers M₉ with adder D₁₄ for generating the signal A_(1j) and toa set of multipliers M₁₀ with adder D₁₅ for generating the signalA_(2j). The arrangement of adders D₁₃, D₁₄, D₁₅ and multipliers M₉, M₁₀is identical to the arrangement of adders D₀, D₁, D₂ and multipliers M₁,M₂ of FIG. 1.

The mapper of FIG. 3, which is designed for q=4, comprises threequantizer-subtracter combinations Q₁−S₇, Q₂−S₈, Q₃−S₉ and a finalquantizer Q₄. Each of the quantizers is a 1-bit quantizer, which outputsone bit of the q-bit output sequence. In each of the combinations thesubtracter calculates the difference between the input and the output ofthe quantizer. The difference signal of the first combination Q₁−S₇ isweighed in a multiplier M₁₁ and the so weighed difference signal isapplied as input signal to the second combination Q₂−S₈. The differencesignal of the first combination and the difference signal of the secondcombination are each weighed in a multiplier M₁₂ and M₁₃ respectivelyand added in an adder D₁₆. The output of this adder constitutes theinput signal of the third combination. The difference signal of thefirst, second and third combinations are each weighed in a multiplierM₁₄, M₁₅ and M₁₆ respectively and added in an adder D₁₇ to constitutethe input signal of the final quantizer Q₄. Preferably, the multipliersM₁₁, M₁₃ and M₁₆ have the same weighing factor and also the multipliersM₁₂ and M₁₅ have the same weighing factor. The values of the weighingfactors may be calculated with the algorithm shown in theabove-mentioned article in “Int. Journal of Circuit Theory andApplications”, vol. 25, pp. 419–437, 1997.

In the reverse Rebic algorithm the mapping process is not free of errorswith the consequence that the signals A_(0j), A_(1j) and A_(2j), whichare fed back, are also not free of errors. This is the basic reason thatformulas (4a) and (4b) cannot be applied in a reverse Rebic algorithmand therefore it is not possible to make a reverse Rebic structure withone integrator less than the order of the Rebic is.

As with the structure of the forward Rebic, also the reverse Rebicstructure of FIG. 2 can be modified in several ways. An example thereofis given in FIG. 3, which comes in place of the elements S₆, F, M₆, D₈,D₉ and I₆ of FIG. 2. The arrangement comprises an integrator I₇ with twoinput signals b_(j)−A_(2j) and −r_(1j)−T_(1j). For the input signalb_(j)−A_(2j) the integrator operates as a delaying integrator withz-transform 1/(z-1). For the input signal −r_(1j)−T_(1j) the integratoroperates as a non-delaying integrator with z-transform z/(z-1). Theoutput signal of the integrator I₇ is:b_((j-1))−A_(2(j-1))−r_(1j)−T_(1j)−r_(2(j-1))=−r_(2j).

As indicated above, the algorithm as defined in the formulas sheet isbased on a low pass filter function with impulse response

${h(t)} = {{U(t)}{\sum\limits_{m = 0}^{M}{( {\alpha_{m}( {t/T} )} )^{m}.}}}$However, impulse responses with another power series expansion may alsobe used, so that

${{h(t)} = {{U(t)}{\sum\limits_{m = 0}^{M}( {\alpha_{m}( {( {t + {CT}} )/T} )} )^{m}}}},$wherein C is any real constant. For instance, when C=1 the impulseresponse is

${h(t)} = {{U(t)}{\sum\limits_{m = 0}^{M}( {\alpha_{m}( {( {t + T} )/T} )} )^{m}}}$and the formulas of the formulas sheet equally apply, except in that thesummation-borders for the counter n have to be changed as follows:

$\begin{matrix}{\sum\limits_{n = 0}^{{jq} + q - 1}{a_{n}\mspace{11mu}\ldots}} & \;\end{matrix}$in equation (1) should read

${\sum\limits_{n = 0}^{jq}{a_{n}\;\ldots}},{\sum\limits_{n = {jq}}^{{jq} + q - 1}{a_{n}\;\ldots}}$in equations (2), (2a) and (3a) should read

$\sum\limits_{n = {{jq} - q + 1}}^{jq}{a_{n}\;\ldots}$and finally

$\sum\limits_{n = 0}^{{jq} - 1}{a_{n\mspace{14mu}}\ldots}$in equations (2), (2a) and (3b) should read

$\sum\limits_{n = 0}^{{jq} - q}{a_{n\mspace{14mu}}\ldots}$The implication in the structures of FIGS. 1 and 2 is that the weighingfactors of the multiplying sets M₁ and M₉ should be 1, 1+1/q, 1+2/q . .. 2−1/q in stead of 1/q, 2/q, 3/q . . . q/q and that the weighingfactors of the multiplier sets M₂ and M₁₀ should be 1, (1+1/q)²,(1+2/q)². . . (2−1/q)² in stead of (1/q)², (2/q)², (3/q)² . . . (q/q)²

As any higher order feedback system the Rebic system suffers frominstability and this risk is higher the higher the order of the systemis. Because the third order system of FIG. 3 is noise free, this systemis stable and operation is possible without further measures. If noiseis introduced, like it is the case in the reverse mode as a consequenceof the mapping process, the system may be unstable. In fact, the largerthe noise, the higher the instability. This is due to the fact thatinternal noise overloads the loop-quantizer, thereby violating theamplitude and phase margins of the feedback loop. There are twoindependent mechanisms that can be used to control the stability forhigher order systems: a linear one and a non-linear one. In thethird-order example of FIG. 2 the linear one consists in increasing theparameter α₁′. The more increase is made, the more stability isobtained, because the system tends to move from third order towardssecond order behaviour. The non-linear mechanism consists in theintroduction of a clipper G in an integrator, as is shown in FIG. 4.This measure changes the spectral behaviour of the integrator for largesignals into a more direct connection. For effective stability controlboth mechanisms can be applied simultaneously.

Formulas:

$\begin{matrix}{{\sum\limits_{m = 0}^{M}{\alpha_{m}{\sum\limits_{k = 0}^{J}{b_{k}( {j + 1 - k} )}^{m}}}} = {\sum\limits_{m = 0}^{M}{\alpha_{m}{\sum\limits_{n = 0}^{{jq} + q - 1}{a_{n}( {j + 1 - {n/q}} )}^{m}}}}} & (1) \\{{b_{j}{\sum\limits_{m = 0}^{M}\alpha_{m}}} = {{\sum\limits_{m = 0}^{M}{\alpha_{m}{\sum\limits_{n = {jq}}^{{jq} + q - 1}{a_{n}( {j + 1 - {n/q}} )}^{m}}}} + {\sum\limits_{m = 0}^{M}{\alpha_{m}{\sum\limits_{n = 0}^{{jq} - 1}{a_{n}( {j + 1 - {n/q}} )}^{m}}}} - {\sum\limits_{m = 0}^{M}{\alpha_{m}{\sum\limits_{k = 0}^{j - 1}{b_{k}( {j + 1 - k} )}^{m}}}}}} & (2) \\{b_{j} = {{\sum\limits_{m = 0}^{M}{\alpha_{m}^{\prime}{\sum\limits_{n = {jq}}^{{jq} + q - 1}{a_{n}( {j + 1 - {n/q}} )}^{m}}}} + {\sum\limits_{m = 0}^{M}{\alpha_{m}^{\prime}{\sum\limits_{n = 0}^{{jq} - 1}{a_{n}( {j + 1 - {n/q}} )}^{m}}}} - {\sum\limits_{m = 0}^{M}{\alpha_{m}^{\prime}{\sum\limits_{k = 0}^{j - 1}{b_{k}( {j + 1 - k} )}^{m}}}}}} & \text{(2a)} \\{A_{ij} = {\sum\limits_{n = {jq}}^{{jq} + q - 1}{a_{n}( {j + 1 - {n/q}} )}^{i}}} & \text{(3a)} \\{r_{ij} = {{\sum\limits_{n = 0}^{{jq} - 1}{a_{n}( {j + 1 - {n/q}} )}^{i}} - {\sum\limits_{n = 0}^{j - 1}{b_{k}( {j + 1 - k} )}^{i}}}} & \text{(3b)} \\{b_{j} = {\sum\limits_{m = 0}^{M}{\alpha_{m}^{\prime}( {A_{mj} + r_{mj}} )}}} & \text{(3c)} \\{r_{mj} = {\sum\limits_{i = 0}^{m}{\begin{pmatrix}m \\i\end{pmatrix}T_{ij}}}} & \text{(3d)} \\{T_{ij} = {A_{i{({j - 1})}} - b_{j - 1} + r_{i{({j - 1})}}}} & \text{(3e)} \\{b_{j - 1} = {\sum\limits_{m = 0}^{M}{\alpha_{m}^{\prime}( {A_{m{({j - 1})}} + r_{m{({j - 1})}}} )}}} & \text{(4a)} \\{{\sum\limits_{m = 0}^{M}{\alpha_{m}^{\prime}T_{mj}}} = 0} & \text{(4b)}\end{matrix}$b _(j)=α₁′(A _(1j) +r _(1j))+α₂′(a _(2j) +r _(2j))  (5a)b _(j)=α₁′(A _(1j) +T _(0j) +T _(1j))+α₂′(A _(2j) +T _(0j)+2T _(1j) +T_(2j)))  (5b)b _(j)=α₁′(A _(1j) +T _(0j))+α₂′(A _(2j) +T _(0j)+2T _(1j))  (5c)

1. A method of converting the sample rate of a discrete-time inputsignal with sample rate q.f_(s) to a discrete-time output signal with asample rate f_(s) which is a sub multiple of the sample rate of theinput signal (q=integer larger than 1), the method comprising the stepsof series to parallel converting the input signal to generatenon-overlapping words of q samples of the input signal and of processingsaid words at the sub multiple rate f_(s) in accordance with a recursivealgorithm comprising a low-pass filtering function, characterized inthat the algorithm is based on a power-series expansion of theimpulse-response of the low-pass filtering function.
 2. A method ofconverting the sample rate of a discrete-time input signal with samplerate f_(s) to a discrete-time output signal with a sample rate q.f_(s)which is a multiple of the sample rate of the input signal (q=integerlarger than 1), the method comprising the steps of processing said inputsignal at the sample rate f_(s) in accordance with a recursive algorithmcomprising a low-pass filtering function to obtain non-overlapping wordsof q samples of the output signal and of parallel to series convertingsaid words to generate the discrete-time q.f_(s) sample rate outputsignal, characterized in that the algorithm is based on a power-seriesexpansion of the impulse-response of the low-pass filtering function. 3.An apparatus for sample rate conversion for converting the sample rateof a discrete-time input signal with sample rate q.f_(s) to adiscrete-time output signal with a sample rate f_(s) which is a submultiple of the sample rate of the input signal (q=integer larger than1), comprising: means for series to parallel converting the input signalto generate non-overlapping words of q samples of the input signal;means for processing said words at the sub multiple rate f_(s) inaccordance with a recursive algorithm comprising a low-pass filteringfunction, characterized in that the algorithm is based on a power-seriesexpansion of the impulse-response of the low-pass filtering function,said means for processing comprising a number of integrators in cascade.4. The apparatus of claim 3, characterized in that the low passfiltering function is of predetermined order and that the number ofintegrators in said cascade of integrators is one less than the saidpredetermined order.
 5. The apparatus as claimed in claim 3characterized in that at least one of said integrators comprises aclipper.
 6. An apparatus for converting the sample rate of adiscrete-time input signal with sample rate f_(s) to a discrete-timeoutput signal with a sample rate q.f_(s) which is a multiple of thesample rate of the input signal (q=integer larger than 1), comprising:means comprising a number of integrators in cascade for processing saidinput signal at the sample rate f_(s) in accordance with a recursivealgorithm comprising a low-pass filtering function to obtainnon-overlapping words of q samples of the output signal, wherein thealgorithm is based on a power-series expansion of the impulse-responseof the low-pass filtering function; and means for parallel to seriesconverting said words to generate the discrete-time q.f_(s) sample rateoutput signal; and receiving a mapper input signal from said integratorsin cascade and generating said non-overlapping words of q samples of theoutput signal.
 7. The apparatus as claimed in claim 6, characterized inthat said mapper comprises a cascade of quantizer-subtractercombinations, each of said combinations comprising a 1-bit quantizer forgenerating one of the bits of said non-overlapping words of q bits and asubtracter for subtracting the input- and output-signals of the 1-bitquantizer, that the first of said combinations in the cascade receivesthe mapper input signal, that each of the other of said combinations inthe cascade receives a weighed sum of the output signals of thesubtracters of the previous combinations in the cascade and that a finalquantizer receives a weighed sum of the output signals of allsubtracters in the cascade and generates the final bit of said nonoverlapping words of q bits.